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Lazuli
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Interface for Timer/Counter 1 of the ATMega328p. More...
Go to the source code of this file.
Macros | |
Timer/Counter 1 registers definitions. | |
Ordered by address. | |
| #define | TCCR1A DIRECT(0x80) |
| Timer/Counter1 Control Register A. | |
| #define | TCCR1B DIRECT(0x81) |
| Timer/Counter1 Control Register B. | |
| #define | TCCR1C DIRECT(0x82) |
| Timer/Counter1 Control Register C. | |
| #define | TCNT1L DIRECT(0x84) |
| Timer/Counter1 (Low register) | |
| #define | TCNT1H DIRECT(0x85) |
| Timer/Counter1 (High register) | |
| #define | TCNT1 DIRECT_T(0x84, uint16_t) |
| Timer/Counter1 (16-bit register) | |
| #define | ICR1L DIRECT(0x86) |
| Input Capture Register 1 (Low register) | |
| #define | ICR1H DIRECT(0x87) |
| Input Capture Register 1 (High register) | |
| #define | OCR1AL DIRECT(0x88) |
| Output Compare Register 1 A (Low register) | |
| #define | OCR1AH DIRECT(0x89) |
| Output Compare Register 1 A (High register) | |
| #define | OCR1BL DIRECT(0x8a) |
| Output Compare Register 1 B (Low register) | |
| #define | OCR1BH DIRECT(0x8b) |
| Output Compare Register 1 B (High register) | |
| #define | TIMSK1 DIRECT(0x6f) |
| Timer/Counter 1 Interrupt Mask Register. | |
| #define | TIFR1 DIRECT(0x36) |
| Timer/Counter 1 Interrupt Flag Register. | |
Enumerations | |
Timer/Counter 1 registers content. | |
| enum | { TCCR1A_WGM10 = POSITION(0U) , TCCR1A_WGM11 = POSITION(1U) , TCCR1A_COM1B0 = POSITION(4U) , TCCR1A_COM1B1 = POSITION(5U) , TCCR1A_COM1A0 = POSITION(6U) , TCCR1A_COM1A1 = POSITION(7U) } |
| Content of the TCCR1A register. More... | |
| enum | { TCCR1B_CS10 = POSITION(0U) , TCCR1B_CS11 = POSITION(1U) , TCCR1B_CS12 = POSITION(2U) , TCCR1B_WGM12 = POSITION(3U) , TCCR1B_WGM13 = POSITION(4U) , TCCR1B_ICES1 = POSITION(6U) , TCCR1B_ICNC1 = POSITION(7U) } |
| Content of the TCCR1B register. More... | |
| enum | { TCCR1C_FOC1B = POSITION(6U) , TCCR1C_FOC1A = POSITION(7U) } |
| Content of the TCCR1C register. More... | |
| enum | { TIMSK1_TOIE1 = POSITION(0U) , TIMSK1_OCIE1A = POSITION(1U) , TIMSK1_OCIE1B = POSITION(2U) , TIMSK1_ICIE1 = POSITION(5U) } |
| Content of the TIMSK1 register. More... | |
| enum | { TIFR1_TOV1 = POSITION(0U) , TIFR1_OCF1A = POSITION(1U) , TIFR1_OCF1B = POSITION(2U) , TIFR1_ICF1 = POSITION(5U) } |
| Content of the TIFR1 register. More... | |
Interface for Timer/Counter 1 of the ATMega328p.
This file describes the interface of the driver for the "16-bit timer counter 1" of the ATMega328p.
Definition in file timer_counter_1.h.
| #define TCCR1A DIRECT(0x80) |
Timer/Counter1 Control Register A.
Definition at line 32 of file timer_counter_1.h.
| #define TCCR1B DIRECT(0x81) |
Timer/Counter1 Control Register B.
Definition at line 35 of file timer_counter_1.h.
| #define TCCR1C DIRECT(0x82) |
Timer/Counter1 Control Register C.
Definition at line 38 of file timer_counter_1.h.
| #define TCNT1L DIRECT(0x84) |
Timer/Counter1 (Low register)
Definition at line 41 of file timer_counter_1.h.
| #define TCNT1H DIRECT(0x85) |
Timer/Counter1 (High register)
Definition at line 44 of file timer_counter_1.h.
Timer/Counter1 (16-bit register)
Definition at line 47 of file timer_counter_1.h.
| #define ICR1L DIRECT(0x86) |
Input Capture Register 1 (Low register)
Definition at line 50 of file timer_counter_1.h.
| #define ICR1H DIRECT(0x87) |
Input Capture Register 1 (High register)
Definition at line 53 of file timer_counter_1.h.
| #define OCR1AL DIRECT(0x88) |
Output Compare Register 1 A (Low register)
Definition at line 56 of file timer_counter_1.h.
| #define OCR1AH DIRECT(0x89) |
Output Compare Register 1 A (High register)
Definition at line 59 of file timer_counter_1.h.
| #define OCR1BL DIRECT(0x8a) |
Output Compare Register 1 B (Low register)
Definition at line 62 of file timer_counter_1.h.
| #define OCR1BH DIRECT(0x8b) |
Output Compare Register 1 B (High register)
Definition at line 65 of file timer_counter_1.h.
| #define TIMSK1 DIRECT(0x6f) |
Timer/Counter 1 Interrupt Mask Register.
Definition at line 68 of file timer_counter_1.h.
| #define TIFR1 DIRECT(0x36) |
Timer/Counter 1 Interrupt Flag Register.
Definition at line 71 of file timer_counter_1.h.
| anonymous enum |
Content of the TCCR1A register.
Definition at line 84 of file timer_counter_1.h.
| anonymous enum |
Content of the TCCR1B register.
Definition at line 96 of file timer_counter_1.h.
| anonymous enum |
Content of the TCCR1C register.
| Enumerator | |
|---|---|
| TCCR1C_FOC1B | Force output compare for channel A. |
| TCCR1C_FOC1A | Force output compare for channel B. |
Definition at line 109 of file timer_counter_1.h.
| anonymous enum |
Content of the TIMSK1 register.
| Enumerator | |
|---|---|
| TIMSK1_TOIE1 | Overflow interrupt enable |
| TIMSK1_OCIE1A | Output compare A match interrupt enable. |
| TIMSK1_OCIE1B | Output compare B match interrupt enable. |
| TIMSK1_ICIE1 | Input capture enable |
Definition at line 117 of file timer_counter_1.h.
| anonymous enum |
Content of the TIFR1 register.
| Enumerator | |
|---|---|
| TIFR1_TOV1 | Overflow flag |
| TIFR1_OCF1A | Output compare A match flag. |
| TIFR1_OCF1B | Output compare B match flag. |
| TIFR1_ICF1 | Input capture flag |
Definition at line 127 of file timer_counter_1.h.